Protective devices are used in many applications to limit the maximum voltage applied between two junctions of a circuit. For example, protective devices are connected between a gate terminal of a MOS field-effect transistor and a reference terminal (or ground) to protect the gate terminal from excess voltages, which might damage the insulating layer of the MOS transistor.
Typically, protective devices are formed by the back-to-back connection of two Zener diodes. When the voltage applied between the terminals of the protective device exceeds the reverse threshold voltage of one of the Zener diodes, this Zener diode becomes reverse conducting. The other Zener diode is forward conducting. As a result, a substantially constant voltage is maintained at the terminals of the protective device. The voltage level is a value equal to the reverse threshold voltage of the applicable Zener diode.
An example of an integrated structure comprising the protective device described above is illustrated in FIG. 1a. Concentrations of the n-type and p-type impurities are indicated by adding the sign + or the sign - to the letters n and p to indicate respectively, a high or low concentration of impurities. The letters n and p without the addition of the signs + or - indicate concentrations of intermediate value.
The protective structure, indicated by the reference numeral 100, is formed in a chip 105 of semiconductor material doped with n-type impurities. A p-type insulating region 110 delimits two portions 115, 116 of the chip 105. P+type regions 120, 121 are formed in portions 115, 116 respectively. N+ type regions 125, 126 are then formed within the respective regions 120, 121. The upper surface of the chip 105 is coated with an insulating layer 130. Also, there is a metallic track or line 135 which interconnects the regions 120 and 115, the regions 121 and 116, and the insulating region 110. Additional metallic tracks or lines 140, 141 are in contact with the respective regions 125, 126.
The equivalent circuit of the integrated structure described above comprises an n-p-n bipolar transistor Z1 formed by the n-type region 125 (emitter), the p-type region 120 (base) and the n-type region 115 (collector). The base terminal is connected through a resistor R1 to the collector terminal by track 135. Resistor R1 includes the sheet resistance of the region 120. The transistor Z1 forms a Zener diode whose anode and cathode terminals are formed by the respective tracks 135, 140. The transistor Z1 uses the non-destructive reverse breakdown of the surface p-n junction formed by the regions 120 and 125. An additional Zener diode is formed in a similar way by an n-p-n bipolar transistor Z2 having its base terminal connected to the collector terminal through a resistor R2. The collector terminals of the transistors Z1 and Z2 are connected together through the track 135. The tracks 140 and 141 form the external terminals of the protective structure 100.
Various parasitic components are also present in the integrated structure 100. In particular, a p-n-p parasitic transistor Tp1 is formed by the p-type region 121, the n-type region 116 (base) and the p type region 110 (collector). The emitter is in the reverse conducting phase of the transistor Z2. The emitter terminal of the transistor Tp1 is connected to the base terminal of the transistor Z2 (common region 121). The base terminal of the transistor Tp1 is connected to the collector terminal of the transistor Z2 (common region 116), and through the resistor R2 to the base terminal of the transistor Z2 (through the track or line 135).
An n-p-n parasitic transistor Tp2 is also formed by the n-type region 116 (emitter), the p-type region 110 (base) and the n-type region formed by the portion of the chip 105 outside the insulating region 110 (collector). The emitter terminal and the base terminal of the transistor Tp2 are respectively connected to the base terminal (common region 116), and to the collector terminal (common region 110) of the transistor Tp1. The base terminal of the transistor Tp2 is also connected through a resistor R3 to the base terminal of the transistor Tp1. Resistor R3 includes the resistance of the insulating region 110. Similar parasitic components not shown in the figure are associated with the transistor Z1.
Typically, the integrated structure described above is of a mixed signal and power type, in which both low-voltage signal devices and high-voltage power devices are integrated on the same chip 105. For example, reference is made to the circuit illustrated in FIG. 1b. The elements shown previously in FIG. 1a are identified by the same reference numbers or symbols in FIG. 1b. FIG. 1b shows a power device in an emitter-switching configuration comprising a high-voltage bipolar transistor Th and a low-voltage MOS field-effect transistor Ml. The emitter terminal of the high-voltage transistor Th is connected to the drain terminal of the low-voltage transistor Ml. Typically, the source terminal of the low-voltage transistor Ml is connected to a ground terminal. The collector terminal of the high-voltage transistor Th is connected to the first terminal of a load L whose second terminal is connected to the positive terminal of a power supply Vcc. The negative terminal of the power supply Vcc is connected to a ground terminal.
The protective structure 100 is used to limit the maximum (positive and negative) voltage applied to the gate terminal G of the low-voltage transistor Ml by connecting the terminals 140, 141 respectively to the gate terminal G and to a ground terminal. The collector region of the high-voltage transistor Th is formed in the portion of the chip 105 outside the insulating region. Therefore, the collector terminal of the parasitic transistor Tp2 is connected to the collector terminal of the high-voltage transistor Th.
As an illustrative example, the protective structure 100 is activated to limit the voltage between the terminals 140, 141 to a value V1. Consequently, a current I1 flows through the protective structure 100 in the direction shown in the FIG. 1b. In this situation, the transistor Z2 is reverse conducting and the transistor Z1 is forward conducting. The parasitic components associated with the transistor Z1 are negligible in this condition. When the voltage drop across the resistor R2 exceeds the threshold voltage Vbe (typically 0.6 V) of the transistor Tp1, the transistor Tp1 becomes forward conducting. The current supplied by the transistor Tp1 passes through the resistor R3. When the voltage drop across the resistor R3 exceeds the threshold voltage Vbe of the transistor Tp2, the transistor Tp2 also becomes forward conducting. This condition connects the terminal 140 to the portion of the chip 105 outside the insulating region 110.
This situation is particularly dangerous in the case illustrated in FIGS. 1a and 1b since the conduction of the parasitic transistor Tp2 connects the gate terminal G to the collector terminal of the high-voltage transistor Th. When the protective structure 100 is activated to limit the negative voltage at the gate terminal G, the device in an emitter-switching configuration has Th and Ml in a non-conducting state. Therefore, the collector terminal of the high-voltage transistor Th is at a high potential with a value which may be several hundred volts. The application of this voltage to the gate terminal G can therefore cause the destruction of the structure.